The full name of IEEE 1588 is “Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems” (IEEE 1588 Precision Clock Synchronization Protocol), which is simply referred to as Precision Timing Protocol (PTP). Clocks of all nodes in a network are synchronized periodically through a synchronization signal such that systems based on Ethernet achieve precise synchronization and synchronization is realized between each system. Synchronization precision may be in the range of microsecond or even lower.
IEEE 1588 Clock Synchronization generally adopts the Global Navigation Satellite System (GNSS) or Building Integrated Timing System (BITS) clock as a clock source, and provides frequency and phase synchronization for base stations through a Base Station Controller (BSC)/Radio Network Controller (RNC). This solves the problems that traditional wireless services have high cost, inconvenient antenna erection and the like in GNSS frequency synchronization and phase synchronization time services.
The precision of the IEEE 1588 synchronization technology is closely related to the time stamp information carried in the 1588 message; the closer to the real transmitting time the time stamp information is, the higher synchronization precision is. IEEE 1588 protocol (IEEE STD 1588-2008) gives an application example of time stamp, as shown in FIG. 1. Message framing is completed at the application layer of the Ethernet architecture. The time stamp may be added to the 1588 message at any point of the application layer, Media Access Control (MAC) layer (which may be understood as the data link layer) and physical (PHY) layer. It is suggested to complete the time stamp update of the message transmitted out by the application layer through a hardware assist function at the PHY layer. Herein, OS shown in FIG. 1 may be understood as the abbreviation of Operating System.
FIG. 1 is a diagram of 1588 message time stamp processing according to existing technologies. According to the application architecture of FIG. 1, the Central Processing Unit (CPU) of systems such as BSC/RNC completes the receiving and transmitting process of a 1588 message. The 1588 message time stamp update is completed through a hardware assist function such as programmable logic or PHY (as shown in FIG. 2), etc., so that time synchronization of the entire Ethernet system is achieved.
When the CPU of BSC/RNC receives and transmits a message, software interrupt is needed to drive the completion. Limited by the architecture of the CPU processing system, the user capacity loaded by the BSC/RNC serving as the 1588 master clock is limited. At present, in existing IEEE 1588 synchronization technologies, BSC/RNC can merely load dozens of users. Even the specialized high-performance IEEE 1588 synchronization server is difficult to achieve a load of more than 1000 users.
The limit problem for the user capacity loaded by the 1588 master clock of the BSC/RNC system is particularly acute in the large-scale networking applications of femto/micro stations. The incapability of high-capacity intensive time services causes existing femto/micro station networking schemes not to reduce the time service cost to the greatest extent.
In view of the problems of small user capacity of the load and high synchronization cost resulted from the clock synchronization method in the existing technologies, no effective solution has been proposed yet.